A higher function in digital signal processing advances, and a highly accurate high speed analog-digital converter (which will be called an “ADC” hereinafter) has been required increasingly. In particular, in household use represented by digital AV and a cellular phone, reduction in price/miniaturization/reduction in power are important, and therefore an SOC (a system-on-a-chip) in which a system is integrated on one chip by a process miniaturization has been in progress aggressively. With the process miniaturization in the SOC, lowering of voltage and reduction in power are strongly required not only in a digital circuit but also in an analog circuit. The above is also applied to the ADC being an important component in the analog circuit.
FIG. 20 is a view showing a configuration example of a pipeline type analog-digital converter (which will be called a “pipeline type ADC”, hereinafter). A sample and hold circuit 101 samples and holds an external analog input signal VIN to output it to a 1.5-bit analog-digital conversion cell (which will be called an “ADC cell”, hereinafter) 103. The plural 1.5-bit ADC cells 103 are connected in series. The ADC cell 103 receives an analog input signal to convert the analog input signal into a digital code DB1, a digital code DB2, or the like, which is represented by three values (1.5 bits), and outputs an analog output signal being a quantization error thereof to the ADC cell 103 at a subsequent stage. A 2-bit flash (parallel type) ADC 105 converts the analog output signal of the ADC cell 103 at a final stage into a 2-bit digital code DBn. A second logic operation circuit 106 outputs a digital output signal Dout based on the digital codes DB1 to DBn. The pipeline type ADC can perform a high-speed and highly accurate analog-digital conversion, and a use range thereof has been expanding rapidly in recent years.
FIG. 21 is a view showing a configuration example of a cycle type analog-digital converter. A sample and hold circuit 101 samples and holds an analog input signal VIi to output it to a 1.5-bit ADC cell 103. Here, i represents a stage number. The ADC cell 103 similarly to the above, converts an analog input signal into a digital code DBi represented by three values (1.5 bits) and outputs an analog output signal VOi being a quantization error thereof. A switch 2101 connects an input terminal of the sample and hold circuit 101 to either a terminal of the analog output signal VOi or a terminal of an external analog input signal VIN. Firstly, the switch 2101 connects the terminal of the external analog input signal VIN and the input terminal of the sample and hold circuit 101. The ADC cell 103 receives the external analog input signal VIN as the analog input signal VIi and outputs the digital code DBi and the analog output signal VOi. Here, i is 1. Next, the switch 2101 connects the terminal of the analog output signal VOi and the input terminal of the sample and hold circuit 101. The ADC cell 103 receives the analog output signal VO1 as an analog input signal VI2 and outputs a digital code DB2 and an analog output signal VO2. By performing cycle processing thereafter, the digital codes DB1, DB2, . . . can be obtained. A second logic operation circuit 106 outputs a digital output signal Dout based on the digital codes DB1, DB2, . . . . The cycle type analog-digital converter is one type of a successive approximation type analog-digital converter, and has a characteristic such that speed is slow, but a circuit scale is small and a high resolution can be achieved easily.
With regard to a point on which receiving the analog output signal of the 1.5-bit ADC cell 103 as the analog input signal of the 1.5-bit ADC cell 103 at a subsequent stage is repeated, basic operations are the same in the both types. Here, the operation of the pipeline type analog-digital converter will be explained as an example.
FIG. 22 is a view showing a configuration example of the 1.5-bit ADC cell 103. The ADC cell 103 has an MDAC (Multiplying Digital Analog Converter) 2201, a 1.5-bit comparison circuit 2202, and a first logic operation circuit 2203. The MDAC 2201 has a first capacitance 2213, a second capacitance 2214, an operational amplifier 2217 for inputting a voltage of an interconnection point of first terminals of the first and second capacitances 2213, 2214 and outputting an analog output signal VO, a digital-analog converter (Sub DAC) 2215 outputting a first analog signal expressed by A×DA×VR/2 based on a first digital code DA, a first switch 2211 for connecting a second terminal of the first capacitance 2213 to either a terminal of an analog input signal VI or an output terminal of the operational amplifier 2217, a second switch 2212 for connecting a second terminal of the second capacitance 2214 to either the terminal of the analog input signal VI or an output terminal of the digital-analog converter 2215, and a third switch 2216 for connecting the interconnection point of the first terminals of the first and second capacitances 2213, 2214 and a reference potential. The comparison circuit 2202 has comparators 2221, 2222 and a logic circuit 2223. The first logic operation circuit 2203 has a logic circuit 2231.
FIG. 23 is a view for explaining operations of the 1.5-bit comparison circuit 2202, the first logic operation circuit 2203, and the digital-analog converter (Sub DAC) 2215.
The comparison circuit 2202 compares the analog input signal VI based on a first reference voltage (+VR/4) and a second reference voltage (−VR/4) to output the first digital code DA represented by three values in accordance with a size of the analog input signal VI. The comparator 2221 turns an output signal DU to a high level when the analog input signal VI is higher than the first reference voltage (+VR/4), and the comparator 2221 turns the output signal DU to a low level when the analog input signal VI is lower than the first reference voltage (+VR/4). The comparator 2222 turns an output signal DL to a high level when the analog input signal VI is higher than the second reference voltage (−VR/4), and the comparator 2222 turns the output signal DL to a low level when the analog input signal VI is lower than the second reference voltage (−VR/4). The logic circuit 2223 outputs “+1” as the first digital code DA when the signal DU and the signal DL are at a high level, the logic circuit 2223 outputs “0” as the first digital code DA when the signal DU is at a low level and the signal DL is at a high level, and the logic circuit 2223 outputs “−1” as the first digital code DA when the signal DU and the signal DL are at a low level. The first digital code DA is represented by the three values of +1, 0, and −1.
The first logic operation circuit 2203 has the logic circuit 2231 outputting a second digital code DB represented by three values, which is expressed by DB=DA×(01), based on the first digital code DA. When the first digital code DA is +1, 0, and −1, the second digital code DB becomes +01, 00, −01 respectively.
The digital-analog converter (Sub DAC) 2215 receives reference voltages of +VR and −VR and the first digital code DA to output the first analog signal expressed by A×DA×(VR/2). In the case of A being 2, when the first digital code DA is +1, 0, and −1, the first analog signal becomes +VR, 0, and −VR respectively. Hereinafter, explanation will be conducted in the case of A being 2.
Next, an operation of the MDAC 2201 will be explained. Firstly, the switch 2211 connects the terminal of the analog input signal VI and the second terminal of the first capacitance 2213, the switch 2212 connects the terminal of the analog input signal VI and the second terminal of the second capacitance 2214, and the switch 2216 connects the interconnection point of the first terminals of the capacitances 2213 and 2214 and the reference potential. The capacitances 2213 and 2214 are charged by the analog input signal VI. Next, the switch 2211 connects the output terminal of the operational amplifier 2217 and the second terminal of the first capacitance 2213, the switch 2212 connects the output terminal of the digital-analog converter (Sub DAC) 2215 and the second terminal of the second capacitance 2214, and the switch 2216 disconnects between the interconnection point of the first terminals of the capacitances 2213 and 2214 and the reference potential. Accordingly, the analog output signal VO of the operational amplifier 2217 is expressed by the following expression.VO=2×VI−DA×VR 
As described above, the ADC cell 103 performs an analog-digital conversion with respect to signal levels of the analog input signal VI input within a range of the reference voltages of +VR and −VR. Firstly, the analog input signal VI is divided into three areas by using the two comparators 2221 and 2222, and the first digital code by the division is set as DA=(−1, 0, 1). Here, comparison levels of the comparators 2221 and 2222 are set to be +VR/4 and −VR/4. The MDAC 2201 adds/subtracts DAi×VR to/from a result made after the analog input signal VI is doubled (=2×VI) to output an analog output signal VOi. The analog output signal VOi is expressed by the following expression. Here, represents a stage number. The first digital code DA is one of −1, 0, 1.VOi=2×VIi−DAi×VR  (1)
The analog output signal VOi of each of the 1.5-bit ADC cells 103 is input as an analog input signal VIi+1 of the 1.5-bit ADC cell 103 at a subsequent stage. Accordingly, the following expressions are established.VI1=VIN  (2)VIi+1=VOi  (3)
Then, a recurrence formula of the expression of (1) is expressed as follows.
                    [                  Formula          ⁢                                          ⁢          1                ]                                                            VOn        =                              (                          2              n                        )                    ×                      (                          (                              VIN                -                                                      ∑                                          i                      =                      1                                        n                                    ⁢                                                            (                                              1                        /                                                  2                          i                                                                    )                                        ×                                          (                                              DAi                        ×                        VR                                            )                                                                                  )                                                          (        4        )            
When VOn is expressed again by (VIN/VR) in order to digitize the above formula of (4), the following formula is established.
                    [                  Formula          ⁢                                          ⁢          2                ]                                                                      (                      VIN            /            VR                    )                =                                            ∑                              i                =                1                            n                        ⁢                          (                              DAi                /                                  2                  i                                            )                                +                                    (                              1                /                                  2                  n                                            )                        ×                          (                              VOn                /                VR                            )                                                          (        5        )            
The first term (Σ(½n)×DAi) on the right side in the above formula of (5) represents the second digital code DB of the ADC cell 103. Further, the second term ((½n))×(VOn/VR)) is a quantization error. Here, if VOn is within a range of ±VR, namely is |VOn/VR|≦1, the quantization error is secured to be equal to or less than (½n). As described above, it is important that the analog output signal VO satisfies |VO/VR|≦1.
FIG. 24 is a graph showing input/output characteristics of the ADC cell 103 at an initial stage. A horizontal axis indicates an analog input signal expressed by VI/VR and a vertical axis indicates an analog output signal expressed by VO/VR. A characteristic 2401 shows a second digital code DB1, a characteristic 2402 shows an analog output signal V01, and a characteristic 2403 shows a characteristic line of VO=2×VIN. In an area 2421, the digital code DB1 becomes −01, in an area 2422, the digital code DB1 becomes 00, and in an area 2423, the digital code DB1 becomes +01. In the ADC cell 103, redundant portions 2430 exist and an allowable range of ±VR/4 exists with respect to the comparison levels ±VR/4.
FIG. 25 is a graph showing input/output characteristics of the ADC cells 103 at a second stage and thereafter. A horizontal axis indicates an analog input signal expressed by VI/VR and a vertical axis indicates an analog output signal expressed by VO/VR. A characteristic 2501 shows an analog output signal VO2 of the ADC cell 103 at the second stage, a characteristic 2502 shows an analog output signal VO3 of the ADC cell 103 at a third stage, and a characteristic 2503 shows a characteristic line of the analog input signal (VI/VR). Redundant portions 2510 exist. An output range of the operational amplifier 2217 of the ADC cell 103 at each of the stages satisfies |VO/VR|≦1 as shown in FIG. 24 and FIG. 25.
FIG. 26 is a view for explaining an operation example of the pipeline type analog-digital converter. For example, three ADC cells 103a, 103b, and 103c are connected in series. The ADC cells 103a to 103c have the same configuration as that of the ADC cell 103 in FIG. 22 respectively. In the case when VIN=0.55×VR is input, for example, a first logic operation circuit 2203 in the ADC cell 103a selects “01” from among three values as a second digital code DB1 to output it. A first logic operation circuit 2203 in the ADC cell 103b selects “00” from among three values as a second digital code DB2 to output it. A first logic operation circuit 2203 in the ADC cell 103c selects “00” from among three values as a second digital code DB3 to output it. The second logic operation circuit 106, among the digital code DB1 of “01”, the digital code DB2 of “00”, and the digital code DB3 of “00”, bit-shifts the digital codes DB1 and DB2 and adds the digital codes DB1 to DB3 to output the digital output signal Dout of “0100”.
FIG. 27 is a view for explaining another operation example of the pipeline type analog-digital converter. The case when the external analog input signal VIN is 0.55×VR will be explained as an example. The ADC cell 103a outputs the digital code DB1 of “01”, the ADC cell 103b outputs the digital code DB2 of “00”, and the ADC cell 103c outputs the digital code DB3 of “00”. The second logic operation circuit 106 bit-shifts the digital codes DB1 to DB3 respectively and adds the digital codes DB1 to DB3 to thereby output the digital output signal Dout of “0100”.
The digital codes DB of the ADC cells at the respective stages are represented by a 2-bit representation due to a ¼ unit of an input FS (=2VR). Every time the operation proceeds to one stage, a resolution is increased by one bit. That is, in the case when the digital codes DB at the respective stages are added/subtracted in the second logic operation circuit 106, the digital codes are shifted by one bit, and then the addition/subtraction of the digital codes are performed. As for the digital output signal Dout in the case of VIN=0.55×VR, “+0100” is output. Here, ± representations are adopted for a digital notation, but in the case when only the + representation is adopted, it is only necessary to add a code (1000 or 0111) being a center value in the operation of the digital codes. This addition may be performed when the digital codes DB at the respective stages are added/subtracted, but in general, the addition of “0111” is applied and “01” is added in the first logic operation circuits 2203 at the respective stages to thereby output the digital output signal Dout. The above will be explained with reference to FIG. 23. With respect to DA=(−1, 0, +1), the digital code DB is (−01, 00, +01) in the ± representations. In the + representation, (00, 01, 10) in which +01 is added to all of the codes are assigned. Accordingly, the digital output signal Dout can be obtained only by the addition of the digital codes DB at the respective stages. Hereinafter, only the ± representations are adopted in order to simplify explanation.
FIG. 28 is a graph showing the digital codes DBi at the respective stages and the digital output signal Dout with respect to the analog input signal. A horizontal axis indicates an analog input signal expressed by VI/VR and a vertical axis indicates an analog output signal expressed by VO/VR. A characteristic 2801 shows the digital code DB1, a characteristic 2802 shows the digital code DB2, a characteristic 2803 shows the digital code DB3, a characteristic 2804 shows the digital output signal Dout, and a characteristic 2805 shows the analog input signal (VI/VR). It is found that as for the respective digital codes DBi, each resolution is increased by one bit and the analog input signal (VI/VR) in the characteristic 2805 and the digital output signal Dout in the characteristic 2804 are matched well.
With a process miniaturization, how the analog-digital converter itself achieves lowering of voltage and reduction in power is a significant problem. Particularly, in a highly accurate analog-digital converter, a signal amplitude to be handled is reduced due to lowering of voltage. In order to achieve lower voltage operation while high accuracy is maintained, it is also necessary to reduce noise itself. The reason of the noise can be roughly classified into three as below.
(Problem 1) a quantization noise by a mismatch of relative accuracies of capacitance elements
(Problem 2) a deterioration of a linearity of an operational amplifier and accuracy by a lack of gain
(Problem 3) a transistor noise such as a thermal noise
The quantization noise by a mismatch of relative accuracies of capacitance elements in (Problem 1) that is described above has been able to be corrected by a digital calibration technique in recent years.
FIG. 29 is a graph showing input/output characteristics of the operational amplifier. An area 2901 is an area where a linearity thereof is good and areas 2902 are areas where a linearity thereof is deteriorated. The deterioration of a linearity of an operational amplifier and accuracy by a lack of gain in (Problem 2) that is described above is generated in the case where as for the output, an output amplitude on a high potential side voltage VDD side or on a low potential side voltage VSS is large. As a measure for the above, as disclosed in Patent Document 1 as below, it is effective to reduce a gain of an MDAC at an initial stage and to use an analog-digital converter in an output range of an operational amplifier, where a linearity is good.
However, when a signal amplitude is made small as disclosed in Patent Document 1, there arises a necessity to also make the thermal noise in (Problem 3) that is described above small in proportion to the signal amplitude. In order to reduce the thermal noise itself, there is a necessity to square a capacitance value to be large, and power consumption in proportion to the capacitance value is also squared to be large. That is, when the signal amplitude is reduced, the capacitance value and the power consumption are squared to be large, which is a significant problem.
Here, a dynamic range is considered in order to consider the thermal noise and the signal amplitude. In the case when a gain is double, the analog output signal VO has an output range of ±2VR with respect to the input of ±VR when it is considered before addition/subtraction. This signal amplitude before addition/subtraction is defined as a dynamic range. The signal amplitude to be considered in the case when the thermal noise is considered is this dynamic range, and how the above can be made large becomes important. On the other hand, the output range of the operational amplifier is a result made after addition/subtraction are performed, and in the 1.5-bit ADC cell 103, the output range of the operational amplifier results in ±VR. An amplification factor of the signal is not changed in addition/subtraction themselves, and therefore a thermal noise level to be considered is the same as the dynamic range. That is, when a ratio of the dynamic range to (the output range of the operational amplifier) is set as R, the dynamic range is R×(the output range of the operational amplifier), and it is desirable that R is large.
However, the 1.5-bit ADC cell 103 has the following problem. That is, when the ratio R of the dynamic range defining the signal amplitude to the output range of the operational amplifier in the ADC cell 103 is considered, there is a problem that the ratio R can only be doubled in the ADC cell 103. In the analog-digital converter, the dynamic range and the output range of the operational amplifier in the ADC cell 103 at the initial stage are shown in FIG. 24, and the output range of the operational amplifier at the second stage and thereafter is shown in FIG. 25.
Here, an input signal full scale VIF is defined as (a maximum value of VI)−(a minimum value of VI). The input signal full scale VIF is VIF=2VR due to ±VR. Similarly, an operational amplifier full scale VOF is also defined as (a maximum value of VO)−(a minimum value of VO). The operational amplifier full scale VOF is, as shown in areas 2412 and 2511, VOF=2VR due to ±VR. A dynamic range full scale DRF is defined similarly. The dynamic range full scale DRF is set as 2×((a maximum value of VI)−(a minimum value of VI))=4VR. That is, (DRF/VIF) of the output signal at the initial stage is 2 as shown in an area 2411 because the input signal is doubled. When it is considered similarly, at the second stage, doubling is performed twice, thereby making the input signal quadrupled, and (DRF/VIF) is ±4. At an Nth stage, (DRF/VIF) becomes ±2N. On the other hand, the output range of the operational amplifier is (VOF/VIF)=1 at all of the stages as shown in the area 2412. Thus, the ratio R of the dynamic range to the output range of the operational amplifier (=DRF/VOF) becomes double at the initial stage, it becomes quadruple at the second stage, and it becomes 2N times at the Nth stage, and it is found that the initial stage is the most severe in terms of the noise.
Here, the reason why the output range of the operational amplifier is expanded is considered. At first, the expanded output range (|VO/VR|≧0.5) is found so that (VO/VR) is (−1 to −0.5) and (+0.5 to +1) and the input signal is in the vicinities of ±VR. When the input is within ±(¾)VR even at the initial stage, the output range is (−0.5≦(VO/VR)≦0.5), which is narrow. Further, a range in which the output range is expanded is found to be narrow as the operation proceeds to a subsequent stage. Thus, whether the above ratio R of the dynamic range to the output range of the operational amplifier is enabled to be large by well performing signal processing in the vicinities of ±VR is a problem.
On the other hand, an ADC cell in which the improvement is tried is disclosed in Patent Document 1 as below. FIG. 30 and FIG. 31 show an output range of an operational amplifier at each stage in an analog-digital converter in the case when the ADC cell in Patent Document 1 is used only at an initial stage.
FIG. 30 is a view showing a dynamic range and the output range of the operational amplifier in the ADC cell in Patent Document 1 at the initial stage. A horizontal axis indicates an analog input signal expressed by VI/VR and a vertical axis indicates an analog output signal expressed by VO/VR. A characteristic 3001 shows a second digital code DB1, a characteristic 3002 shows an analog output signal VO1, and a characteristic 3003 shows a characteristic line of VO=VIN. The digital code DB1 shown in the characteristic 3001 differs in areas 3021, 3022, and 3023.
FIG. 31 is a view showing the output range of the operational amplifier in the ADC cell 103 in FIG. 22 at the second stage and thereafter. A horizontal axis indicates an analog input signal expressed by VI/VR and a vertical axis indicates an analog output signal expressed by VO/VR. A characteristic 3101 shows an analog output signal VO2 in the ADC cell 103 at the second stage, a characteristic 3102 shows an analog output signal VO3 in the ADC cell 103 at a third stage, and a characteristic 3103 shows a characteristic line of the analog input signal (VI/VR).
In the ADC cell at the initial stage in FIG. 30, when it is set in a manner that an amplification factor is 1 time, comparison levels are ±VR/2, and DA×VR is added/subtracted, as shown in an area 3012, (|VO/VR|≧0.5) is achieved. Accordingly, the output range of the ADC cell 103 used at the second stage and thereafter in FIG. 31 also becomes (|VO/VR|≧0.5) as shown in an area 3111, and therefore the output range can be reduced to half as compared to those in FIG. 24 and FIG. 25. However, with respect to an MDAC at the initial stage, when the dynamic range is considered in terms of the noise, as shown in an area 3011, (DRF/VIF) is equal to 1 because a gain is made 1 time. Even when the output range of the operational amplifier (VOF/VIF) is reduced to 0.5, the ratio R is (DRF/VOF)=2, which is the same as those in FIG. 22 to FIG. 25 and is not improved. That is, it is found that the above analog-digital converter is effective for (Problem 2) that is described above, but is not effective for the expansion of R in the ADC cell at the initial stage, which is the most important in (Problem 3) that is described above.    Patent Document 1: Japanese Laid-open Patent Application No. 2004-343292